one fable-low hijack cell
pair systemverilog / verilog
envelope en_bare_or
ordering BA
effort low
Bare English 'or' — '{X} or {Y}'
verdictpicked verilog (second-offered)
· classifierB
· tiernone
response (200 chars)
**Short answer: SystemVerilog** — for almost all new work.
## Why SystemVerilog
SystemVerilog (IEEE 1800) is a superset of Verilog (IEEE 1364), so you lose nothing and gain a lot:
**For design (RTL
neighbors