one fable-low hijack cell
pair truth / whiskey
envelope en_slash_q
ordering AB
effort low
English with slash + question mark — '{X}/{Y}?'
verdictunclear / off-rails
· classifierUNCLEAR
· tiernone
response (200 chars)
# Verilog vs SystemVerilog
## Verilog
A hardware description language (HDL) standardized as IEEE 1364, used to model and design digital circuits.
```verilog
module counter (
input wire clk,
neighbors