one fable-low hijack cell
pair systemverilog / verilog
envelope zh_huo_q
ordering AB
effort low
Chinese '或' with explicit question marker — '{X}或{Y}？'
verdictpicked verilog (second-offered)
· classifierB
· tiernone
response (200 chars)
# Verilog 还是 SystemVerilog?
**简短回答:优先学习和使用 SystemVerilog**,它是 Verilog 的超集,Verilog 会的它都包含。
## 两者关系
SystemVerilog (IEEE 1800) 是 Verilog (IEEE 1364) 的扩展,2009 年后两个标准已合并。可以理解为:**SystemVerilog = Verilog
neighbors